The present disclosure generally relates to memory systems, and memory controllers that control the operation of memory devices in such systems. Specific embodiments described herein refer to methods and apparatus for types of memory device access during calibration operations, as executed by a memory controller.
In multi-rank memory systems, memory devices are organized into two or more ranks of memory where each rank of memory devices is independently addressable by a memory controller. Memory controllers write data to and read data from the memory devices in a rank through a data bus. In multi-rank memory systems, data buses are a shared resource. For example, devices in separate memory ranks may be connected to and share a common data bus. The memory controller transfers data with one memory rank at a time through the data bus.
Signaling interfaces in the memory controller and memory devices are responsible for transmitting signals to and receiving signals from the data bus. Due to the high-frequency nature of modern memory signaling, these interfaces are sensitive to changes in voltage and temperature. The signaling interfaces can be periodically calibrated to compensate for such changes. In conventional multi-rank memory systems, the signaling interfaces are calibrated one rank at a time. However, calibration operations tie up an entire data bus and block data access to the memory devices of other ranks that are not being calibrated.